The Intel Core Duo processor (previously codenamed Yonah) was Intel’s first mobile dual-core processor built on the company’s next generation 65nm process technology. This has enabled a pair of Yonah cores to be fit onto a die only slightly larger than the previous Dothan-cored Pentium M (90mm2 compared to 84mm2 for the older part). The relatively small increase in die size and total transistor count (up around 11 million to approaching 152 million) is largely explained by the fact that most of the area of the die is taken up by the same 2MB of Level 2 cache.
In addition to the new mobile dual-core architecture, the Intel Core Processor includes several innovative features. These include a number of changes which together eliminate limitations that have restricted the Pentium M’s multimedia performance relative to that of NetBurst architecture-based chips. Referred to a Digital Media Boost, these include instruction optimisations and performance enhancements for existing Streaming SIMD Extensions 2 (SSE2), 13 new Streaming SIMD Extensions 3 (SSE3) instructions and enhancements to floating point instruction decoding performance that will allow multiple SSE instructions to be handled in parallel.
Another new feature is a shared 2MB Level 2 cache which enables an active execution core to access the full 2MB cache when the other execution core is idle. Dubbed Smart Cache, this uses dynamic cache allocation across both cores to enhance performance and reduce cache under-utilisation and misses. Efficient data sharing between both cores minimises FSB traffic and reduces cache coherency complexity and the processor’s enhanced Data Pre-fetch Logic speculatively fetches data to the L2 cache before cache requests occur, thereby reducing bus cycle penalties.
In the past the design of mobile processing platforms have required a trade off between performance and battery life. In the case of the Core Duo, the design goal was breakthrough performance while at the same time optimising energy efficiency and enabling longer battery life. The result is that each of the CPU’s execution cores is able to independently and dynamically transition to Halt, Stop Clock, and Deep Sleep low-power states, so that if only one core is being utilised, the second core can still enter an idle state to help save power. Moreover, Dynamic Power Co-ordination also enables co-ordinated transitions to Deeper Sleep and an Enhanced Deeper Sleep mode, for example when the Smart Cache dynamically flushes the cache to system memory during periods of inactivity.
The following table identifies the various Core Duo models and their principal characteristics:
| Processor Number | Cache | Clock Speed | Front Side Bus | Power |
|---|---|---|---|---|
| T2700 | 2 MB L2 | 2.33 GHz | 667 MHz | 31W |
| T2600 | 2 MB L2 | 2.16 GHz | 667 MHz | 31W |
| T2500 | 2 MB L2 | 2.00 GHz | 667 MHz | 31W |
| T2400 | 2 MB L2 | 1.83 GHz | 667 MHz | 31W |
| T2300 | 2 MB L2 | 1.66 GHz | 667 MHz | 31W |
| T2300E | 2 MB L2 | 1.66 GHz | 667 MHz | 31W |
| L2400 | 2 MB L2 | 1.66 GHz | 667 MHz | 15W |
| L2300 | 2 MB L2 | 1.50 GHz | 667 MHz | 15W |
| U2500 | 2 MB L2 | 1.20 GHz | 533 MHz | 9.0W |